pulp-platform/ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

What it solves

Ara provides a high-performance, energy-efficient hardware implementation of the RISC-V Vector Extension (version 1.0). It serves as a vector coprocessor for the CVA6 core, enabling the execution of data-parallel workloads that would be inefficient on a standard scalar processor.

How it works

Ara is implemented as a vector unit that works alongside a scalar core. It utilizes a scalable architecture that supports multiprecision floating-point operations and can be configured for different performance needs. The project provides a full toolchain, including an LLVM-based compiler and the Spike ISA simulator, to develop and test applications. It can be simulated using Verilator or ModelSim and can be deployed on FPGAs (such as VCU128 and VCU118) in both bare-metal and Linux environments.

Who it’s for

This project is designed for hardware engineers, computer architects, and researchers focusing on RISC-V development, vector processing, and the design of energy-efficient AI and computing accelerators.

Highlights

  • RISC-V V 1.0 Compliant: Full support for the standardized RISC-V Vector Extension.
  • Flexible Configuration: Centralized parameters allow users to customize the vector machine configuration.
  • Comprehensive Tooling: Includes integrated support for LLVM toolchains, Spike simulation, and RTL simulation via Verilator.
  • FPGA Ready: Supports implementation on Xilinx VCU128 and VCU118 boards.
  • Performance Analysis: Supports VCD dumping for activity-based power analysis on specific kernels like FFT and fmatmul.

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