THU-DSP-LAB/ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

What it solves

Ventus provides an open-source General-Purpose Graphics Processing Unit (GPGPU) design. It addresses the need for high-performance, open-source hardware capable of handling vector computations and high-performance computing (HPC) tasks, specifically targeting the RISC-V ecosystem.

How it works

Ventus is developed using Chisel HDL and is based on the RISC-V ISA with the RVV (RISC-V Vector) extension. It implements a SIMT (Single Instruction, Multiple Threads) architecture. The project includes a full-stack approach: a hardware design that can be deployed on FPGAs, an LLVM-based OpenCL C compiler, an ISA simulator, and a driver. It utilizes a memory hierarchy including private memory, local shared memory within Streaming Multiprocessors (SM), and global memory accessed via an L2 cache.

Who it’s for

This project is designed for hardware architects, researchers in high-performance computing, and developers interested in open-source GPGPU design and RISC-V vector extensions.

Highlights

  • RISC-V Based: Leverages the RISC-V ISA and its vector extension (RVV) for general-purpose computing.
  • Full-Stack Toolchain: Includes an LLVM-based OpenCL C compiler and a dedicated driver.
  • FPGA Ready: Provides tools to generate Verilog files specifically for deployment on FPGA hardware.
  • SIMT Support: Implements branching and warp execution logic essential for GPGPU workloads.

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