ucb-bar/chipyard

What it solves

Chipyard is designed to simplify the agile development of custom systems-on-chip (SoCs) based on Chisel. It provides a unified framework that integrates various processor cores, accelerators, and tooling to move from design to implementation more efficiently.

How it works

It leverages the Chisel hardware description language (HDL) and the Rocket Chip SoC generator to produce RISC-V SoCs. The framework integrates several key components:

• Processor Cores: Includes support for Rocket, BOOM, and CVA6 (Ariane).
• Vector Units: Integrates Saturn and Ara vector units.
• Accelerators: Includes AI-focused accelerators like Gemmini and NVDLA.
• Memory and Peripherals: Provides memory systems and MMIO-mapped peripherals.
• Development Flows: Supports software RTL simulation, FPGA-accelerated simulation via FireSim, automated VLSI flows via Hammer, and software workload generation via FireMarshal.

Who it’s for

Hardware architects, VLSI designers, and researchers focusing on RISC-V and custom SoC development.

Highlights

• Integrated Ecosystem: Combines cores, vector units, and accelerators into a single framework.
• Agile Hardware Development: Supports multiple concurrent flows from simulation to VLSI implementation.
• ** uma RISC-V Base**: Built around the RISC-V instruction set architecture.
• Comprehensive Tooling: Includes specialized tools for simulation (FireSim) and automated VLSI flows (Hammer).