usamahz/cpu-performance-engineering

What it solves

This project provides a rigorous, evidence-based curriculum for understanding how modern CPUs execute code at the instruction level. It addresses the gap between high-level programming and the physical reality of hardware, helping developers identify exactly where performance bottlenecks occur and how to prove that a specific optimization is effective.

How it works

It organizes technical literature, vendor manuals, and research papers into a logical reading order, starting from basic computer architecture and moving toward advanced topics like cache hierarchy, branch prediction, and multi-socket NUMA systems. Crucially, it emphasizes "proof" over theory: fourteen sections include runnable C-based microbenchmarks that allow users to measure hardware behavior themselves. It also includes an MCP (Model Context Protocol) server, which allows AI coding assistants to query this curated knowledge base and provide answers backed by specific technical sources.

Who it’s for

This is for systems engineers, performance engineers, and developers working on low-latency applications, high-performance computing, or CPU-bound inference tasks who need to understand the "mechanical sympathy" between their code and the underlying silicon.

Highlights

• Curated list of primary sources (papers, specifications, and vendor manuals) for x86 and Arm server architectures.
• Includes 14 runnable microbenchmarks with raw data and analysis to verify hardware behavior.
• Provides an MCP server to integrate this performance knowledge directly into AI coding tools like Claude Desktop or Cursor.
• Strictly scoped to CPU-level performance, excluding higher-level abstractions like database internals or language runtimes.