ucb-bar/gemmini

What it solves

Gemmini provides a full-system, full-stack platform for exploring and evaluating Deep Neural Network (DNN) hardware. It allows architects to analyze how different components of the system and software stack—beyond just the accelerator itself—interact to impact overall DNN performance.

How it works

Gemmini is implemented as a RoCC (Rocket Custom Coprocessor) accelerator for RISC-V, developed using the Chisel hardware description language. Its architecture centers around a systolic array for matrix multiplications, supporting both output-stationary and weight-stationary dataflows.

Key hardware components include:

• Decoupled Access/Execute Architecture: Separate controllers for execute, load, and store instructions allow memory access and computation to happen concurrently.
• Scratchpad and Accumulator: Private SRAMs used to store inputs, partial sums, and final results.
• DMA Engine: Facilitates data transfer between the host CPU's main memory and the accelerator's private SRAMs.
• Peripheral Circuitry: Supports activation functions (like ReLU), scaling for quantized workloads, and matrix transposition.

Who it’s for

It is designed for hardware architects and researchers who want to build, configure, and profile diverse DNN accelerators and test them using functional simulators (Spike) or cycle-accurate simulators (Verilator, VCS, and FireSim).

Highlights

• Flexible Configuration: Parameters can be tuned for systolic array dimensions, dataflows, memory capacity, and data types (e.g., 8-bit integers or floating point).
• Full-Stack Evaluation: Integrates with the Chipyard ecosystem to test software binaries in baremetal, Linux, or proxy-kernel environments.
• Hardware-Software Co-design: Includes a library (libgemmini) and test suite for running large DNN models like ResNet50.
• FPGA Acceleration: Supports FireSim for high-speed, cycle-accurate simulation of end-to-end workloads.