Micron Drops 4F² DRAM After Two Decades of Research: Why It's Sticking With 6F² and Betting on 3D DRAM

Micron is abandoning 4F² DRAM after more than two decades of research, with President and CTO Scott DeBoer saying the geometry delivers no meaningful density advantage over the existing 6F² layout while sharply increasing manufacturing cost and complexity. The decision, announced at a Micron technology webinar that laid out the company's future roadmap, makes Micron the only major DRAM maker stepping back from 4F² while Samsung, SK hynix, and China's CXMT push ahead with it.

Micron is ditching 4F² DRAM and staying on 6F²

Micron has ended its long-running effort to commercialize 4F² DRAM and will continue building memory cells on the established 6F² geometry for the foreseeable future. The company says it invested "over two decades" of research into 4F², a layout that promises a theoretical 33% density improvement over 6F².

Micron's roadmap instead focuses on aggressively scaling 6F²: high-density 1δ (1-delta) memory is ramping yields, 1-ε (1-epsilon) with advanced wafer bonding is in development, and the company lists "ζÅ" (zeta-Angstrom) and "ηÅ" (eta-Angstrom) as its future for planar DRAM. Micron's Boise campus, recently the site of a $50B expansion, will produce 1δ memory.

4F² and 6F² describe cell geometry, not process nodes

4F² and 6F² are DRAM cell geometries, not logic process nodes. They describe the shape and layout of a DRAM cell rather than its physical size, which is set by the combination of layout and process node.

DRAM does not use the same node nomenclature as logic because each DRAM cell contains both a transistor and a capacitor, which complicates scaling. DRAM vendors mark generational changes with labels such as 1γ (gamma) and 1δ (delta) — Greek letters used to signify serial improvements over time.

Micron's CTO says capacitor spacing, not cell footprint, sets DRAM density

Scott DeBoer, Micron's President and CTO, argues that DRAM density is ultimately determined by the spacing required by the capacitors, not by the nominal cell footprint. Shrinking the geometry from 6F² to 4F² looks like an easy density win on paper, but according to DeBoer it does not actually gain much density and it drastically increases cost and complexity.

DeBoer noted that Micron "invented" 4F² and that the company spent "over two decades" trying to figure out how to commercialize the technology before discarding it. Tom's Hardware framed the same conclusion in its headline on the roadmap, describing the architecture as offering no meaningful density advantages while increasing manufacturing complexity and costs and carrying fundamental scaling limitations.

3D DRAM is Micron's real long-term target

Micron says the real future of DRAM is 3D DRAM: memory devices in which multiple physical layers of DRAM storage cells are stacked vertically on top of each other. This is distinct from simply stacking DRAM on top of logic, which is what Micron refers to as wafer bonding.

Flash memory has been stacking cells in three dimensions for more than a decade, but flash relies on simple charge-trap transistors that can be stacked like the floors of a skyscraper. DRAM cells are dynamic: each bit requires a delicate, high-aspect-ratio capacitor paired with a transistor that inevitably leaks charge. Flipping those tall capacitors sideways and scaling them vertically without thermal crosstalk or signal destruction requires a total overhaul of the basic DRAM architecture.

That transition will not happen overnight, but as 2D scaling hits its absolute physical limit, 3D DRAM is where the industry is headed.

Samsung, SK hynix, and CXMT are still pursuing 4F²

All three of Micron's major competitors — Samsung, SK hynix, and CXMT — are moving ahead with 4F² designs. CXMT in particular has claimed it will have 4F² RAM in server DDR5 RDIMMs by the end of the year.

In the short term, Micron could face challenges if its competitors are able to economically manufacture 4F² memory at scale. Micron is placing a large strategic wager that 4F² will prove to be a costly, short-lived detour. If Samsung, SK hynix, or CXMT burn billions in capital expenditure adopting vertical-channel transistors only to hit an early brick wall in capacitor scaling, Micron's decision to skip the transition will look prescient. By extracting remaining efficiency from established 6F² lithography using High-NA EUV, advanced materials, and wafer-on-wafer bonding through the zeta and eta eras, Micron aims to preserve cash and engineering bandwidth for being first across the finish line when monolithic 3D DRAM becomes economically viable.

Hacker News commenters are skeptical of the framing

The most upvoted line of criticism on Hacker News questioned whether Micron's announcement is a strategy or a reframing of a competitive disadvantage.

Sounds rather more like a company behind the innovation curve pretending to "skip" the innovation as if to jump into a better innovation. When the actual truth is they are sticking with the old thing. Reframed as a choice. If "Ditching 4f" is such a good idea, why show their hand right before their competitors make the foolish choice of releasing it? Why not hold your cards until afterwards? Unless perhaps this isn't a brilliant strategy but instead a spin for the investors?

A separate comment argued that current DRAM markups make further research spending unnecessary: "At the markups they are making they could be hand-soldering the bits and still be ahead, scaling existing process makes more sense than investing more in research."

Another commenter was pessimistic that any near-term process change will move DRAM economics much, writing that they "still dont see any major breakthrough in near future we could bring the BOM cost of DRAM down to below $1/GB. Not even 4F^2 would do that."

Two comments addressed presentation and supply. One noted that the roadmap image "looks like mojibake," joking that they would be "excited to buy 6F²ζÅ DRAM but I assume it's going to be reserved for AI datacentres that don't exist." Another was disappointed that the article did not include a diagram comparing the two cell layouts, writing: "Disappointing that they didn't toss in an image showing the difference between 6T and 4T."

Key facts at a glance

Micron is abandoning 4F² DRAM after more than two decades of research and will continue with 6F².
4F² offers a theoretical 33% density improvement over 6F², but Micron says capacitor spacing, not cell footprint, governs real density.
Micron's roadmap targets 1δ (ramping yields), 1-ε (advanced wafer bonding, in development), then ζÅ and ηÅ for planar DRAM.
Micron's Boise campus, site of a $50B expansion, will produce 1δ memory.
Samsung, SK hynix, and CXMT are all continuing with 4F²; CXMT claims 4F² server DDR5 RDIMMs by the end of the year.
Micron's long-term bet is monolithic 3D DRAM, which requires a full architectural overhaul because DRAM cells pair a leaking transistor with a high-aspect-ratio capacitor.