robertcprice/nCPU

nCPU: model-native and tensor-optimized CPU research runtimes with organized workloads, tools, and docs

What it solves

It reimagines the computer as a differentiable entity, replacing traditional hardware logic and operating system components with trained neural networks or GPU-accelerated kernels. This allows programs to be discovered via gradient descent rather than written by hand and enables the creation of a computer substrate that is immune to timing side-channel attacks.

How it works

The project implements a full execution stack across three modes:

  • Neural Mode: Every layer—from ALU operations (addition, multiplication) to the OS (memory management, scheduling) and the display—is a trained neural network. This makes the entire pipeline from source code to pixels differentiable.
  • Compute Mode: A high-performance implementation using Rust and Metal shaders that executes ARM64 instructions on a GPU, allowing it to boot a UNIX OS, run a self-hosting C compiler, and load real Linux binaries like BusyBox and Alpine Linux.
  • Fast Mode: Uses native tensor operations to maintain differentiability while improving speed.

Additionally, it includes nSynth for program synthesis from I/O examples, a differentiable coprocessor that can be injected into LLMs to improve arithmetic accuracy, and a JEPA-style world model that predicts machine state transitions in a latent space.

Who it’s for

  • AI researchers exploring differentiable computing and program synthesis.
  • Security researchers interested in constant-time execution and side-channel immunity.
  • Developers interested in the intersection of neural networks and low-level systems architecture.

Highlights

  • Neural ALU: Achieves 100% accuracy on 32-bit integer arithmetic.
  • GPU-Native OS: Runs a multi-process UNIX OS and a self-hosting C compiler entirely on a GPU.
  • Differentiable Synthesis: Discovers executable programs from examples using gradient descent.
  • LLM Enhancement: Improves arithmetic accuracy in Qwen models (e.g., +56.5 pp for Qwen3.5-2B) via a neural ALU coprocessor.
  • Timing Immunity: Zero cycle-count variance (σ = 0.0), making it resistant to cache-timing attacks for cryptography.

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