The-OpenROAD-Project/OpenROAD

What it solves

OpenROAD provides an open-source, autonomous flow for semiconductor digital design, removing the high cost and schedule risk associated with traditional integrated circuit (IC) design. It enables a "No-Human-In-Loop" (NHIL) process to rapidly move from Register Transfer Level (RTL) descriptions to a final physical layout (GDSII) in as little as 24 hours.

How it works

OpenROAD implements a complete physical design flow consisting of several automated stages:

• Synthesis: Converts RTL into a gate-level netlist.
• Floorplanning: Defines chip area, utilization, and power distribution networks (PDN).
• Placement: Handles global and detailed placement of macros and standard cells, including optimization for timing and capacitance.
• Clock Tree Synthesis (CTS): Inserts buffers and resizes nets to optimize clock distribution.
• Routing: Performs global and detailed routing to connect components while adhering to design rules.
• Finishing: Conducts parasitic extraction, final timing verification, and generates the GDSII layout file.

The system is PDK-independent and can be controlled via an API with bindings for Tcl and Python, or through pre-configured flow scripts.

Who it’s for

• Hardware Designers: For rapid architecture and design space exploration.
• Researchers & Students: For low-cost access to IC design software and education.
• VLSI Enthusiasts: For those performing open-source tapeouts.
• Industry Collaborators: For commercial applications requiring rapid physical implementation.

Highlights

• Autonomous Flow: Delivers a full RTL-to-GDSII implementation without human intervention.
• Broad PDK Support: Validated with open-source (e.g., SKY130, GF180) and proprietary PDKs (down to 12nm).
• Proven Track Record: Used in over 600 silicon-ready tapeouts.
• Integrated GUI: Includes a powerful visualization tool for debugging floorplans, congestion, and routing.