RISCBoy Open-Source Portable RISC‑V Game Console Overview

RISCBoy Open-Source Portable RISC‑V Game Console Overview

RISCBoy delivers a full handheld game console on a single low‑cost FPGA

RISCBoy is a completely open‑source portable games console that implements a custom RISC‑V CPU, raster graphics pipeline, and full peripheral infrastructure on an iCE40‑HX8k FPGA, proving that a 32‑bit gaming system can fit into a tiny, affordable device.

Core Architecture: RISC‑V CPU, Bus Fabric, and Graphics

RISCBoy integrates a RV32IMC‑compatible processor that passes the official RISC‑V compliance suite and formal verification checks. The CPU includes M‑mode CSRs, exception handling, and a vectored interrupt extension, providing a solid foundation for game software.

The system bus is an AHB‑lite crossbar with APB peripherals (UART, GPIO, SPI, PWM, etc.), enabling efficient communication between the CPU, memory controllers, and custom graphics unit.

The graphics pipeline is a scanline‑buffer‑based raster engine that drives a display controller, as described in the project's PDF documentation. This design mirrors the classic Game Boy Advance rendering approach but is implemented entirely in synthesizable Verilog 2005.

FPGA Target: iCE40‑HX8k Constraints and Toolchain

The entire console fits into a Lattice iCE40‑HX8k FPGA (7680 logic elements). Achieving this density required careful RTL design and resource‑aware coding practices.

Open‑source toolchain: Synthesis uses Yosys, place‑and‑route uses nextpnr, and bitstream generation relies on Project Icestorm. These tools run on Linux and can even be built on a Raspberry Pi.

Alternative FPGA support: Experimental builds exist for Lattice ECP5 (LEF5UM5G‑85F‑EVN), swapping the external 512 KiB SRAM for an internal 256 KiB 32‑bit synchronous memory.

Software Stack: RV32IMC Toolchain and Test Suites

RV32IMC GNU toolchain: The project provides instructions to build a custom RISC‑V GNU toolchain configured for the RV32IMC ISA (‑‑with‑arch=rv32imc, ‑‑with‑abi=ilp32). The multilib setup generates standard libraries for all supported ISA variants, preventing mismatches between compiled binaries and the processor configuration.

Testing: The repository includes HDL‑level regression tests and software tests that run on the simulator. The simulation flow uses Xilinx ISIM 14.x on Linux, with makefiles in the scripts/ directory. Tests can be launched via ./runtests after initializing submodules.

PCB Design and Production

KiCad PCB layout: RISCBoy’s Rev A board is a 5 × 5 cm, 4‑layer design compatible with iTead’s prototyping service (≈ $65 for 10 boards). The schematic is available as a PDF (board/fpgaboy.pdf).

Future revisions: Rev B is pending until the gateware and bootloader mature, and the developer’s current hardware resembles the Snowflake FPGA board.

Repository Structure for Easy Navigation

  • board/ – KiCad files for the main PCB and auxiliary boards.
  • doc/ – LaTeX sources and PDFs for documentation, including the detailed system architecture diagram.
  • hdl/ – Verilog RTL:
    • busfabric/ – AHB‑lite crossbar and APB peripherals.
    • graphics/ – Pixel processing unit.
    • hazard5/ – Self‑contained RV32IMC core.
    • mem/ – Memory controllers and models.
    • peris/ – Small peripherals (UART, SPI, PWM).
    • riscboy_core/ – Top‑level integration of all components.
    • riscboy_fpga/ – Board‑specific wrappers for different FPGA targets.
  • synth/ – Makefiles and constraint files for full‑system synthesis.
  • test/ – Verilog testbenches and software test cases.
  • software/ – Collection of C files used for system‑level tests.

Community Reception and Notable Mentions

“It is a Gameboy Advance from a parallel universe where RISC‑V existed in 2001. A love letter to the handheld consoles from my childhood, and a 3 AM drunk text to the technology that powered them.” – Project description.

“Oh this is Luke Wren’s work. He’s an ASIC design engineer at Raspberry Pi. Amazing project, I love it!” – HN comment highlighting the author’s credentials.

“The programmable scanline‑buffer‑based rendering pipeline described in the PDF is worth a read for fans of such things.” – HN comment praising the graphics design.

“The design was taped out on the first wafer.space run, but I have not heard if it actually worked or not.” – HN comment noting a silicon prototype attempt.

Getting Started: Clone, Build, and Synthesize

# Clone with submodules
git clone --recursive https://github.com/Wren6991/RISCBoy.git riscboy

# Build the RV32IMC toolchain (Ubuntu 20.04 example)
sudo apt install -y autoconf automake autotools-dev curl python3 \
    libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex \
    texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev
cd /tmp
git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain
./configure --prefix=/opt/riscv \
    --with-arch=rv32imc --with-abi=ilp32 \
    --with-multilib-generator="rv32i-ilp32--;rv32ic-ilp32--;rv32im-ilp32--;rv32imc-ilp32--"
sudo mkdir /opt/riscv && sudo chown $(whoami) /opt/riscv
make -j$(nproc)

# Synthesize for HX8k evaluation board
. sourceme
cd synth
make -f HX8k-EVN.mk bit

Why RISCBoy Matters

RISCBoy demonstrates that a fully featured 32‑bit handheld gaming system can be realized with open‑source hardware, a modest FPGA, and freely available toolchains. It provides a complete reference design—from silicon‑level RTL to PCB layout—enabling hobbyists, educators, and researchers to explore RISC‑V based game console architectures without proprietary constraints.

Sources